1. Technical Field
This disclosure relates to an SIMD-type microprocessor, a method of processing data, an image data processing system, and a method of processing image data.
2. Description of the Related Art
Recently, improvement of image quality, such as increase of the number of picture elements or impartation of a coloring function is intended in an image processing device such as a digital copying machine or a facsimile apparatus. Then, the number of data that should be processed increases with the improvement of image quality.
Meanwhile, in regard to data processing in an image processing device such as a copying machine, identical processing operations are frequently applied to all of the picture elements. Therefore, an SIMD-type microprocessor is frequently used in which identical processing operations are simultaneously applied to plural data by one command.
FIG. 1 illustrates an SIMD-type microprocessor according to a related art. An SIMD-type microprocessor 100 illustrated in FIG. 1 is composed of a global processor 101, a processor element group 102, and an external input/output 103, wherein predetermined processing operations are applied to image data read from an image memory 104 connected to the SIMD microprocessor 100.
The global processor 101 is a so-called SISD (Single Instruction-stream, Single Data-stream)-type processor which includes a program RAM and a data RAM, interprets a program, and generates various kinds of control signals. The control signals are also fed to register files or an operation array of the processor element group 102, as described below, as well as included blocks. Furthermore, the GP (global processor) conducts various kinds of processing operations and a program control operation using an included generalized register, ALU (arithmetic and logic unit) and the like at the time of executing a command.
In the processor element group 102, plural register files 102a are arranged linearly and plural operation parts 102b are also arranged linearly. On the register files 102a, data to be proceeded by processor elements are held. The control of data reading from/writing into the register files 102a is conducted through controlling of the global processor 101. The data read by controlling the global processor 101 are sent to the operation parts 102b, subjected to processing operations on the operation parts 102b, and subsequently written into the register files 102a. Furthermore, the register files 102a are accessible from the outside of the SIMD-type microprocessor 100 and reading/writing of a specified register is/are conducted from the outside besides the control of the global processor 101. On the operation parts 102b, processing operations are conducted according to a PE (processor element) command. All of the controls of the processing operations according to the PE command are conducted through the global processor 101.
On the external input/output 103, original image data to be processed are read from the image memory 104 and written into the register files 102a of the processor element group 102 or processed image data are read from the register files 102a and written into the read image memory 104.
On the image memory 104, original image data to be processed are stored and processed image data are also stored.
When the number of PEs (the number of the register files 102a and operation parts 102b) is increased in order to improve the throughput of the SIMD-type microprocessor 100 as described above, the length of a control signal line extending from a driving circuit of a PE control signal generator included in the global processor or the like to the terminal of the processor element group 102 (signal line for conducting the control of processing operations according to a PE command) becomes very long.
For example, as described with reference to FIG. 2, the difference between the delay times of a PED arranged near the global processor 101 in the processor element group 102 and a PEn arranged at the end terminal (the most remote one) is large due to the difference between the lengths of wires of the control signal lines and therefore it may be difficult to increase the operation frequency relating to the throughput.
Against such a problem, for example, a method as disclosed in Japanese Patent Application Publication H08-212169 has been suggested. Japanese Patent Application Publication H08-212169 discloses an array processor in which registers between adjacent n processor elements are grouped and a common bus is set to provide each group with one control signal line.
In the method as disclosed in Japanese Patent Application Publication No. H08-212169, however, there is a problem that it may be difficult to connect the registers between the adjacent processor elements by means of a read bus and write bus so as to conduct, for example, a process for shifting plural processor elements, rewriting the data of a specified processor element, or the like. Furthermore, the wiring delay between the control signals for a processor element near a command sequence control part and an end terminal processor element has not been taken into consideration in the method as disclosed in Japanese Patent Application Publication No. H08-212169. Therefore, it has been difficult to increase the operation frequency relating to the throughput.